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? 2005 integrated device technology, inc. dsc-6527/1 idt and the idt logo are trademarks of integrated device technology, inc. 1 july, 2005 octal t1/e1 short haul analog front end idt82v2048l functional block diagram figure-1 block diagram slicer peak detector line driver waveform shaper los detector one of eight identical channels register file control interface clock generator mode[2:0] cs ts2/sclk/ale/ as ts1/ rd /r/ w ts0/sdi/ wr / ds sdo/rdy/ ack int d[7:0]/ad[7:0] mc[3:0]/a[4:0] mclk trst tck tms tdi tdo jtag tap rtipn rringn ttipn tringn vddio vddt vddd vdda losn rcn rdpn rdnn tclkn tdnn tdpn g.772 monitor transmit all ones oe clke features ! octal t1/e1 short haul analog front end which supports 100 ? t1 twisted pair, 120 ? e1 twisted pair and 75 ? e1 coaxial applications ! built-in transmit pre-equaliz ation meets g.703 & t1.102 ! digital/analog los detector meets itu g.775, ets 300 233 and t1.231 ! itu g.772 non-intrusive monitori ng for in-service testing for any one of channel 1 to channel 7 ! low impedance transmit drivers with high-z ! selectable hardware and parallel/serial host interface ! hitless protection switching (hps) for 1 to 1 protection without relays ! jtag boundary scan for board test ! 3.3 v supply with 5 v tolerant i/o ! low power consumption ! operating temperat ure range: -40 c to +85 c ! available in 144-pin thin quad flat pack (tqfp) and 160-pin plastic ball grid array (pbga) packages green package options available
2 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges pin configurations figure-2 tqfp144 package pin assignment idt82v2048l (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 tdp7 tclk7 los6 rdn6 rdp6 rc6 tdn6 tdp6 tclk6 mclk mode2 a4 mc3/a3 mc2/a2 mc1/a1 mc0/a0 vddio gndio vddd gndd d0/ad0 d1/ad1 d2/ad2 d3/ad3 d4/ad4 d5/ad5 d6/ad6 d7/ad7 tclk1 tdp1 tdn1 rc1 rdp1 rdn1 los1 tclk0 tdn3 rc3 rdp3 rdn3 los3 rtip3 rring3 vddt3 ttip3 tring3 gndt3 rring2 rtip2 gndt2 tring2 ttip2 vddt2 rtip1 rring1 vddt1 ttip1 tring1 gndt1 rring0 rtip0 gndt0 tring0 ttip0 vddt0 mode1 los0 rdn0 rdp0 rc0 tdn0 tdp0 tdp4 tclk4 los5 rdn5 rdp5 rc5 tdn5 tdp5 tclk5 tdi tdo tck tms trst ic ic vddio gndio vdda gnda mode0 cs ts2/sclk/ale/ as ts1/ rd /r/ w ts0/sdi/ wr / ds sdo/rdy/ ack int tclk2 tdp2 tdn2 rc2 rdp2 rdn2 los2 tclk3 tdp3 tdn4 rc4 rdp4 rdn4 los4 oe clke vddt4 ttip4 tring4 gndt4 rtip4 rring4 gndt5 tring5 ttip5 vddt5 rring5 rtip5 vddt6 ttip6 tring6 gndt6 rtip6 rring6 gndt7 tring7 ttip7 vddt7 rring7 rtip7 los7 rdn7 rdp7 rc7 tdn7
3 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges figure-3 pbga160 package pin assignment vddt 4 tring 4 gndt 4 rtip 4 rtip 7 gndt 7 tring 7 vddt 7 rdn 7 rc4 rdp 4 rdn 4 rdp 7 rc7 vddt 5 tring 5 gndt 5 rtip 5 rtip 6 gndt 6 vddt 6 rdn 6 rc5 rdp 5 rdn 5 rdp 6 rc6 vddt 5 ttip 5 gndt 5 rring 5 rring 6 gndt 6 ttip 6 vddt 6 tdn 6 tclk 5 tdp 5 tdn 5 tdp 6 tclk 6 los 4 los 7 los 6 oe clke los 5 mode 2 mclk tms a4 mc 3 tck tdo tdi mc 2 mc 1 gndio gndio mc 0 vddio ic trst d0 vddio gnda gndd d1 vdda ic mode 0 d2 vddd cs d3 d4 ts 0 ts 1 ts 2 d5 d6 los 3 los 0 los 1 sdo int los 2 mode 1 d7 vddt 2 ttip 2 gndt 2 rring 2 rring 1 gndt 1 ttip 1 vddt 1 tdn 1 tclk 2 tdp 2 tdn 2 tdp 1 tclk 1 vddt 2 tring 2 gndt 2 rtip 2 rtip 1 gndt 1 tring 1 vddt 1 rdn 1 rc2 rdp 2 rdn 2 rdp 1 rc1 vddt 3 ttip 3 gndt 3 rring 0 gndt 0 ttip 0 vddt 0 tdn 0 tclk 3 tdp 3 tdn 3 tdp 0 tclk 0 vddt 3 tring 3 gndt 3 rtip 3 rtip 0 gndt 0 tring 0 vddt 0 rdn 0 rc3 rdp 3 rdn 3 rdp 0 rc0 vddt 7 ttip 7 gndt 7 rring 7 rring 4 gndt 4 ttip 4 vddt 4 tdn 4 tclk 7 tdp 7 tdn 7 tdp 4 tclk 4 tring 6 idt82v2048l (bottom view) rring 3 a b c d e f g h j k l m n p a b c d e f g h j k l m n p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14
4 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges 1 pin description table-1 pin description name type pin no. description tqfp144 pbga160 transmit and receive line interface ttip0 ttip1 ttip2 ttip3 ttip4 ttip5 ttip6 ttip7 tring0 tring1 tring2 tring3 tring4 tring5 tring6 tring7 analog output 45 52 57 64 117 124 129 136 46 51 58 63 118 123 130 135 n5 l5 l10 n10 b10 d10 d5 b5 p5 m5 m10 p10 a10 c10 c5 a5 ttipn/tringn: transmit bipolar tip/ring for channel 0~7 these pins are the differential line driver outputs. they will be in high impedance state if pin oe is low or the corresponding pin tclkn is low (pin oe is global control, while pin tclkn is per-channel control). in host mode, each pin can be in high impedance by programming a ?1? to the corresponding bit in register oe (1) . rtip0 rtip1 rtip2 rtip3 rtip4 rtip5 rtip6 rtip7 rring0 rring1 rring2 rring3 rring4 rring5 rring6 rring7 analog input 48 55 60 67 120 127 132 139 49 54 61 66 121 126 133 138 p7 m7 m8 p8 a8 c8 c7 a7 n7 l7 l8 n8 b8 d8 d7 b7 rtipn/rringn: receive bipolar tip/ring for channel 0~7 these pins are the differential line receiver inputs. 1 . register name is indicated by bo ld capital letter. for example, oe indicates output enable register.
5 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges transmit and receive digital data interface tdp0 tdp1 tdp2 tdp3 tdp4 tdp5 tdp6 tdp7 tdn0 tdn1 tdn2 tdn3 tdn4 tdn5 tdn6 tdn7 i 37 30 80 73 108 101 8 1 38 31 79 72 109 102 7 144 n2 l2 l13 n13 b13 d13 d2 b2 n3 l3 l12 n12 b12 d12 d3 b3 tdpn/tdnn: positive/negative transmit data for channel 0~7 the nrz data to be transmitted for positive/negative pulse is input on this pin. data on tdpn/tdnn are active high and are sampled on the falling edges of tclkn. tclk0 tclk1 tclk2 tclk3 tclk4 tclk5 tclk6 tclk7 i 36 29 81 74 107 100 9 2 n1 l1 l14 n14 b14 d14 d1 b1 tclkn: transmit clock for channel 0~7 the clock of 1.544 mhz (for t1 mode) or 2.048 mhz (for e1 mode) for transmit is input on this pin. the transmit data at tdpn or tdnn is sampled into the device on the falling edges of tclkn. different combinations of tclkn and mclk result in different transmit mode. it is summarized as table-2 system interface configuration . rdp0 rdp1 rdp2 rdp3 rdp4 rdp5 rdp6 rdp7 rdn0 rdn1 rdn2 rdn3 rdn4 rdn5 rdn6 rdn7 o high imped- ance 40 33 77 70 111 104 5 142 41 34 76 69 112 105 4 141 p2 m2 m13 p13 a13 c13 c2 a2 p3 m3 m12 p12 a12 c12 c3 a3 rdpn/rdnn: positive/negative receive data for channel 0~7 these pins output the raw rz sliced data. the active polarity of rdpn/rdnn is determined by pin clke. when pin clke is low, rdpn/rdnn is active low. when pin clke is high, rpdn/rdnn is active high. rdpn/rdnn will remain active duri ng los. rdpn/rdnn is set into high impedance when the correspond- ing receiver is powered down. rc0 rc1 rc2 rc3 rc4 rc5 rc6 rc7 o high imped- ance 39 32 78 71 110 103 6 143 p1 m1 m14 p14 a14 c14 c1 a1 rcn: receive pulse for channel 0~7 rcn is the output of an internal exclusive or (xor) which is connected with rdpn and rdnn. the clock is recovered from the signal on rcn. if receiver n is powered down, the corresponding rcn will be in high impedance. table-1 pin description (continued) name type pin no. description tqfp144 pbga160 tdpn tdnn output pulse 0 0 space 0 1 negative pulse 1 0 positive pulse 1 1 space
6 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges mclk i 10 e1 mclk: master clock this is an independent, free running reference clock. a clock of 1.544 mhz (for t1 mode) or 2.048 mhz (for e1 mode) is supplied to this pin as the clock reference of the device for normal operation. when mclk is low, all the receivers are powered down, and the output pins rcn, rdpn and rdnn are switched to high impedance. in transmit path, the operation mode is decided by the combination of mclk and tclkn (see table-2 system interface configuration for details). note: wait state generation via rdy/ ack is not available if mclk is not provided. los0 los1 los2 los3 los4 los5 los6 los7 o 42 35 75 68 113 106 3 140 k4 k3 k12 k11 e11 e12 e3 e4 losn: loss of signal output for channel 0~7 a high level on this pin indicates the loss of signal when there is no transition over a specified period of time or no enough ones density in the received signal. the transition will return to low automatically when there is enough transitions over a specified period of time with a certain ones density in the received sig- nal. the los assertion and desertion criteria are described in 2.4.3 loss of signal (los) detection . hardware/host control interface mode2 i (pulled to vddio/2) 11 e2 mode2: control mode select 2 (2) the signal on this pin determines which control mode is selected to control the device: hardware control pins include mode[2:0], ts[2:0], clke and oe. serial host interface pins include cs , sclk, sdi, sdo and int . parallel host interface pins include cs , a[4:0], d[7:0], wr / ds , rd /r/ w , ale/ as , int and rdy/ ack . the device supports multiple parallel host interface as follows ( refer to mode1 and mode0 pin descriptions below for details ): mode1 i 43 k2 mode1: control mode select 1 (2) in parallel host mode, the parallel interface operates with separate address bus and data bus when this pin is low, and operates with multiplexed address and data bus when this pin is high. in serial host mode or hardware mode, this pin should be grounded. mode0 i 88 h12 mode0: control mode select 0 (2) in parallel host mode, the parallel host interface is configured for motorola compatible hosts when this pin is low, or for intel compatible hosts when this pin is high. in serial host mode or hardware mode, this pin should be grounded. cs i (pulled to vddio/2) 87 j11 cs : chip select (active low) in host mode, this pin is asserted low by the host to enable host interface. a high to low transition must occur on this pin for each read/write operation and the level must not return to high until the operation is over. in hardware control mode, this pin should be pulled to vddio/2. table-1 pin description (continued) name type pin no. description tqfp144 pbga160 mode2 control interface low hardware mode vddio/2 serial host interface high parallel host interface mode[2:0] host interface 100 non-multiplexed motorola mode interface 101 non-multiplexed intel mode interface 110 multiplexed motorola mode interface 111 multiplexed intel mode interface 2 . in host mode, register e-afe has to be set to ?ffh? for proper device operation. see expanded register description on page 28 for more details.
7 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges ts2/sclk/ ale/ as i86j12 ts2: template select 2 in hardware control mode, the signal on this pin is the most significant bit for the transmit template select. refer to 2.5.1 waveform shaper for details. sclk: shift clock in serial host mode, the signal on this pin is the shift clock for the serial interface. data on pin sdo is clocked out on falling edges of sclk if pin clke is high, or on rising edges of sclk if pin clke is low. data on pin sdi is always sampled on rising edges of sclk. ale: address latch enable in parallel intel multiplexed host mode, the address on ad[4:0] is sampled into the device on the falling edges of ale (signals on ad[7:5] are ignored). in non-multiplexed host mode, ale should be pulled high. as : address strobe (active low) in parallel motorola multiplexed host mode, the address on ad[4:0] is latched into the device on the falling edges of as (signals on ad[7:5] are ignored). in non-multiplexed host mode, as should be pulled high. ts1/ rd /r/ w i85j13 ts1: template select 1 in hardware control mode, the signal on this pin is the second most significant bit for the transmit template select. refer to 2.5.1 waveform shaper for details. rd : read strobe (active low) in parallel intel multiplexed or non-multiplexed host mode, this pin is active low for read operation. r/ w : read/write select in parallel motorola multiplexed or non-multiplexed host mode, the pin is active low for write operation and high for read operation. ts0/sdi/ wr / ds i84j14 ts0: template select 0 in hardware control mode, the signal on this pin is the least significant bit for the transmit template select. refer to 2.5.1 waveform shaper for details. sdi: serial data input in serial host mode, this pin input the data to the serial interface. data on this pin is sampled on the rising edges of sclk. wr : write strobe (active low) in parallel intel host mode, this pin is active low during write operation. the data on d[7:0] (in non-multi- plexed mode) or ad[7:0] (in multiplexed mode) is sampled into the device on the rising edges of wr . ds : data strobe (active low) in parallel motorola host mode, this pin is active low. during a write operation (r/ w = 0), the data on d[7:0] (in non-multiplexed mode) or ad[7:0] (in multiplexed mode) is sampled into the device on the rising edges of ds . during a read operation (r/ w = 1), the data is driven to d[7:0] (in non-multiplexed mode) or ad[7:0] (in multiplexed mode) by the device on the rising edges of ds . in parallel motorola non-multiplexed host mode, the address information on the 5 bits of address bus a[4:0] are latched into the device on the falling edges of ds . table-1 pin description (continued) name type pin no. description tqfp144 pbga160
8 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges sdo/rdy/ ack o83k14 sdo: serial data output in serial host mode, the data is output on this pin. in serial write operation, sdo is always in high imped- ance. in serial read operation, sdo is in high impedance only when sdi is in address/command byte. data on pin sdo is clocked out of the device on the falling edges of sclk if pin clke is high, or on the rising edges of sclk if pin clke is low. rdy: ready output in parallel intel host mode, the high level of this pin reports to the host that bus cycle can be completed, while low reports the host must insert wait states. ack : acknowledge out put (active low) in parallel motorola host mode, the low level of this pin indicates that valid information on the data bus is ready for a read operation or acknowledges the acceptance of the written data during a write operation. int o open drain 82 k13 int : interrupt (active low) this is an open drain, active low interrupt output. two sources may cause the interrupt. refer to 2.19 inter- rupt handling for details. d7/ad7 d6/ad6 d5/ad5 d4/ad4 d3/ad3 d2/ad2 d1/ad1 d0/ad0 i/o high imped- ance 28 27 26 25 24 23 22 21 k1 j1 j2 j3 j4 h2 h3 g2 dn: data bus 7~0 in non-multiplexed host mode, these pins are the bi-directional data bus. adn: address/data bus 7~0 in multiplexed host mode, these pins are the multiplexed bi-directional address/data bus. in hardware mode, these pins should be tied to vddio/2. in serial host mode, these pins should be grounded. table-1 pin description (continued) name type pin no. description tqfp144 pbga160
9 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges a4 mc3/a3 mc2/a2 mc1/a1 mc0/a0 i 12 13 14 15 16 f4 f3 f2 f1 g3 mcn: performance monitor configuration 3~0 in hardware control mode, a4 must be connected to gnd. mc[3:0] are used to select a transmitter or receiver of channel 1 to 7 for non-intrusive monitoring. channel 0 is used as the monitoring channel. if a transmitter is monitored, signals on the correspondi ng pins ttipn and tringn are internally transmitted to rtip0 and rring0 pins. if a receiver is monitored, signals on the corresponding pins rtipn and rringn are internally transmitted to rtip0 and rring0 pins. the monitored is then output to rdp0 and rdn0 pins. performance monitor configuration determined by mc[3:0] is shown below. note that if mc[2:0] = 000, the device is in normal operation of all the channels. in host mode operation, the monitoring channel is selected in the pmon register. the signals monitored by channel 0 can be routed to ttip0/ring0 by activa ting the remote loopback in this channel (refer to 2.13 g.772 monitoring ). an: address bus 4~0 when pin mode1 is low, the parallel host interface operates with separate address and data bus. in this mode, the signal on this pin is the address bus of the host interface. when pin mode1 is high or in serial host mode, these pins should be tied to gnd. oe i 114 e14 oe: output driver enable pulling this pin low can drive all driver output into high impedance for redundancy application without external mechanical relays. in this condition, all other internal circuits remain active. clke i 115 e13 clke: clock edge select the signal on this pin determines the active edge of rcn, rdpn, rdnn and sclk. refer to 2.3 clock edges for details. jtag signals trst i pull-up 95 g12 trst : jtag test port reset (active low) this is the active low asynchronous reset to the jtag test port. this pin has an internal pull-up resistor and can be left disconnected. tms i pull-up 96 f11 tms: jtag test mode select the signal on this pin controls the jtag test performance and is clocked into the device on the rising edges of tck. this pin has an internal pull-up resistor and can be left disconnected. tck i 97 f14 tck: jtag test clock the clock of the jtag test is input on this pin. the data on tdi and tms are clocked into the device on ris- ing edges of tck while the data on tdo pin is clocked out of the device on falling edges of tck. this pin should be connected to gndio or vddio pin when unused. table-1 pin description (continued) name type pin no. description tqfp144 pbga160 mc[3:0] monitoring configuration 0000 normal operation without monitoring 0001 monitor receiver 1 0010 monitor receiver 2 0011 monitor receiver 3 0100 monitor receiver 4 0101 monitor receiver 5 0110 monitor receiver 6 0111 monitor receiver 7 1000 normal operation without monitoring 1001 monitor transmitter 1 1010 monitor transmitter 2 1011 monitor transmitter 3 1100 monitor transmitter 4 1101 monitor transmitter 5 1110 monitor transmitter 6 1111 monitor transmitter 7
10 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges tdo o high imped- ance 98 f13 tdo: jtag test data output the serial data of the jtag test is output on this pin. the data on tdo pin is clocked out of the device on the falling edges of tck. tdo is a high impedance output signal. it is active only when scanning of data is over. this pin should be left float when unused. tdi i pull-up 99 f12 tdi: jtag test data input the serial data of the jtag test is input on this pin. the data on tdi pin is clocked into the device on the rising edges of tck. this pin has an internal pull-up resistor and it can be left disconnected. power supplies and grounds vddio - 17 92 g1 g14 3.3 v i/o power supply gndio - 18 91 g4 g11 i/o gnd vddt0 vddt1 vddt2 vddt3 vddt4 vddt5 vddt6 vddt7 - 44 53 56 65 116 125 128 137 n4, p4 l4, m4 l11, m11 n11, p11 a11, b11 c11, d11 c4, d4 a4, b4 3.3 v/5 v power supply for transmitter driver all vddt pins must be connected to 3.3 v or all vddt must be connected to 5 v. it is not allowed to leave any of the vddt pins open (not-connected) even if the channel is not used. t1 is only 5v vddt. gndt0 gndt1 gndt2 gndt3 gndt4 gndt5 gndt6 gndt7 - 47 50 59 62 119 122 131 134 n6, p6 l6, m6 l9, m9 n9, p9 a9, b9 c9, d9 c6, d6 a6, b6 analog gnd for transmitter driver vddd vdda - 19 90 h1 h14 3.3 v digital/analog core power supply gndd gnda - 20 89 h4 h11 digital/analog core gnd others ic - 93 g13 ic: internal connection internal use. leave it open for normal operation. ic - 94 h13 ic: internal connection internal use. leave it open for normal operation. table-1 pin description (continued) name type pin no. description tqfp144 pbga160
11 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges 2 functional description 2.1 overview the idt82v2048l is a fully int egrated octal short-haul analog front end (afe), which contains eight transmit and receive channels for use in either t1 or e1 applications. the raw sliced data (no retiming) is output to the system. transmit equalizati on is implemented with low-impedance output drivers that prov ide shaped waveforms to the transformer, guar- anteeing template conformance. mor eover, testing functions, such as jtag boundary scan is provided. the device is optimized for flexible software control through a serial or parallel host mode interface. hard- ware control is also available. figure-1 on page 1 shows one of the eight identical channels operation. 2.2 t1/e1 mode selection t1/e1 mode selection configures the device globally. in hardware control mode, the template selection pins ts[2:0], determine whether the operation mode is t1 or e1 (see table-5 on page 14 ). in software mode, the register ts determines whether the operation mode is t1 or e1. 2.2.1 system interface the system interface of each channel operates in dual rail mode with data recovery, that is, with raw data slicing only and without clock recovery. the dual rail interface consist of tdpn 1 , tdnn, tclkn, rdpn, rdnn and rcn. data transmitted from tdpn and tdnn appears on ttipn and tringn at the line interface. the interface of the afe is shown in figure-4 . pin rdpn and rdnn, are raw rz slice outputs and internally connected to an xor which is fed to the rcn output for external clock reco very applications. 2.2.1.1 system interface configuration for normal transmit and receive operat ion, the device is configured as follows: in host mode, mclk can be either clocked or pulled high. if mclk is pulled high, tclk1 has to be prov ided for proper device operation. in addition, register e-afe 2 has to be set to ?ffh? to ensure proper device operation. see expanded register description on page 28 for details. in hardware mode, mclk has to be pulled high and tclk1 has to be provided for proper device operation. depending on the state of tclk1 and tclkn, the transmitter will transmit all ones (taos), will go into power down, or will go into high impedance. the status of tclk1 and tclkn has no effect on the receive paths. by setting mclk low, all the receive paths are powered down. table-2 summarizes the different combinations between mclk and tclkn. 1. the footprint ?n? (n = 0 - 7) indicates one of the eight channels. 2. the first letter ?e-? in dicates expanded register.
12 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges figure-4 analog front end (afe) interface table-2 system inte rface configuration host or hardware mode mclk tclk1 tclkn afen in e-afe transmitter mode transmit and receive normal operation host (1) only 1. in host mode, register e-afe must be set to ?ffh? for proper operation. see expanded register description on page 28 for details. clocked clocked clocked 1 normal operation host or hardware (2) 2. in hardware mode, mclk must be pulled high and tclk1 provided for proper operation. high clocked clocked dc (3) 3. dc means don?t care normal operation transmit interface modes host only clocked high ( 16 mclk) 1 transmit all ones (taos) signals to the line side in the corresponding transmit channel. low ( 64 mclk) corresponding transmit channel is set into power down state. host or hardware high/low tclk1 is clocked tclkn is high ( 16 tclk1) dc transmit all ones (taos) signals to the line side in the corre- sponding transmit channel. tclkn is low ( 64 tclk1) corresponding transmit channel is set into power down state. tclk1 is unavailable. dc all eight transmitters (ttipn & tringn) are in high imped- ance. receive interface modes host or hardware low the receive path is not affected by the status of tclk1 or tclkn. dc all the receive paths are powered down. slicer peak detector line driver waveform shaper los detector one of eight identical channels rtipn rringn ttipn tringn losn rcn rdpn rdnn tclkn tdnn tdpn transmit all ones
13 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges 2.3 clock edges the active edge of sclk is selectable. if pin clke is high, the active edge of sclk is the falling edge. on the contrary, if clke is low, the active edge sclk is the rising edge. pi n sdo is always active high, and the output signals are valid on the active edge of sclk. see table-3 active clock edge and active level for details. pin clke is used to set the active level for rdpn/rdnn raw slicing output: high for active high polarity and low for active low. it should be noted that data on pin sdi are always active high and are samp led on the rising edges of sclk. the data on pin tdpn or tdnn are also always active high but are sampled on the falling edges of tclkn, despite the level on clke. 2.4 receiver in receive path, the line signals couple into rringn and rtipn via a transformer and are converted into rz digital pulses by a data slicer. adaptation for attenuation is achiev ed using an integral peak detector that sets the slicing levels. the recovered data on pin rdpn/rdnn in an undecoded dual rail rz format. loss of signal is detected. this change in status may be enabled to generate an interrupt. 2.4.1 peak detector and slicer the slicer determines the pres ence and polarity of the received pulses. the raw positive slicer output appears on rdpn while the nega- tive slicer output appears on rdnn. t he slicer circuit has a built-in peak detector from which the slicing th reshold is derived. the slicing threshold is default to 50% (typical) of the peak value. signals with an attenuation of up to 12 db (from 2.4 v) can be recov- ered by the receiver. to provide i mmunity from impulsive noise, the peak detectors are held above a minimum level of 0.150 v typically, despite the received signal level. 2.4.2 data recovery the analog line signal are converted to rz digital bit streams on the rdpn/rdnn pins and internally connected to an xor which is fed to the rcn output for external cl ock recovery applications. 2.4.3 loss of signal (los) detection the loss of signal detector monitors the amplitude and density of the received signal on receiver line before the transformer (measured on port a, b shown in figure-7 ). the loss condition is reported by pulling pin losn high. at the same time, los alarm registers track los condition. when los is detected or cleared, an interrupt will generate if not masked. in host mode, the detection supports the ansi t1.231 for t1 mode, itu g.775 and etsi 300 233 for e1 mode. in hardware mode, it supports the itu g.775 and ansi t1.231. table-4 summarizes the conditions of los. during los, the rdpn/ rdnn continue to output the sliced data. table-3 active clock edge and active level pin clke pin rdpn and rdnn pin sdo slicer output high active high sclk active high low active low sclk active high table-4 los condition standard signal on losn ansi t1.231 for t1 g.775 for e1 etsi 300 233 for e1 los detected continuous intervals 175 32 2048 (1 ms) high amplitude (1) 1. los levels at device (rtipn, rringn) with all ones signal. for more detail regarding the los parameters, please refer to receiver characteristics on page 38 . below typical 200 mvp below typical 200 mvp below typical 200 mvp los cleared density 12.5% (16 marks in a sliding 128-bit period) with no more than 99 contin- uous zeros 12.5% (4 marks in a sliding 32-bit period) with no more than 15 con- tinuous zeros 12.5% (4 marks in a sliding 32-bit period) with no more than 15 con- tinuous zeros low amplitude (1) exceed typical 250 mvp exceed typical 250 mvp exceed typical 250 mvp
14 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges 2.5 transmitter in transmit path, data in nrz format is clocked into the device on tdpn and tdnn. the data is sampled into the device on falling edges of tclkn. the shape of the pulses are user programmable to ensure that the t1/e1 pulse template is met a fter the signal passes through different cable lengths or types. 2.5.1 waveform shaper t1 pulse template, specified in the dsx-1 cross-connect by ansi t1.102, is illustrated in figure-5 . the device has built-in transmit wave- form templates, corresponding to 5 le vels of pre-equalization for cable of a length from 0 to 655 ft with each increment of 133 ft. e1 pulse template, specified in itu-t g.703, is shown in figure-6 . the device has built-in transmit wave form templates for cable of 75 ? or 120 ? . any one of the six built-in waveforms can be chosen in both hard- ware mode and host mode. in hardware control mode, setting pins ts[2:0] can select the required waveform template for all the transmit- ters, as shown in table-5 . in host mode, the waveform template can be configured on a per-channel basis. bi ts tsia[2:0] in register tsia are used to select the channel and bits ts[2:0] in register ts are used to select the required waveform template. the built-in waveform shaper uses an internal high frequency clock which is 16xmclk as the clock re ference. this function will be bypassed when mclk is unavailable. figure-5 dsx-1 waveform template figure-6 cept waveform template 2.6 line interface circuitry the transmit and receive inte rface rtipn/rringn and ttipn/ tringn connections provide a ma tched interface to the cable. figure-7 shows the appropriate external co mponents to connect with the cable for one transmit/receive channel. table-6 summarizes the component values based on the specific application. -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 0 250 500 750 1000 1250 time (ns) normalized amplitude -300 -200 -100 0 100 200 300 time (ns) -0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20 normalized amplitude table-5 built-in waveform template selection ts2 ts1 ts0 service clock rate cable length maximum cable loss (db) (1) 1. maximum cable loss at 772 khz. 0 0 0 e1 2.048 mhz 120 ? /75 ? cable - - 001 reserved 010 011 t1 1.544 mhz 0-133 ft. abam 0.6 1 0 0 133-266 ft. abam 1.2 1 0 1 266-399 ft. abam 1.8 1 1 0 399-533 ft. abam 2.4 1 1 1 533-655 ft. abam 3.0
15 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges figure-7 external transmit/receive line circuitry 2.7 transmit driver power supply all transmit driver power suppl ies must be 5.0 v or 3.3 v. in e1 mode, despite the power supply voltage, the 75 ? /120 ? lines are driven through a pair of 9.5 ? series resistors and a 1:2 transformer. in t1 mode, only 5.0 v can be selected, 100 ? lines are driven through a pair of 9.1 ? series resistors and a 1:2 transformer. in harsh cable environment, series resistors are requi red to improve the transmit return loss performance and protect the device from surges coupling into the device. 2.8 power driver failure monitor an internal power driver failu re monitor (dfmon), parallel connected with ttipn and tringn, c an detect short circuit failure between ttipn and tringn pi ns. bit scpb in register gcf decides whether the output driver short ci rcuit protection is enabled. when the short circuit protection is enabled, the driver output current is limited to a typical value: 180 map. also, register df , dfi and dfm will be available. when dfmon will detect a short circuit, register df will be set. with a short circuit failure detected, register dfi will be set and an interrupt will be generated on pin int . 2.9 transmit line side short circuit in e1 or t1 with 5 v vddt, a pair of 9.5 ? serial resistors connect with ttipn and tringn pins and limit the output current. in this case, the output current is a limited value which is always lower than the typical line short circuit current 180 map, even if the transmit line side is shorted. refer to table-6 external components values for details. table-6 external components values component e1 t1 75 ? coax 120 ? twisted pair 100 ? twisted pair, vddt = 5.0 v r t 9.5 ? 1% 9.5 ? 1% 9.1 ? 1% r r 9.31 ? 1% 15 ? 1% 12.4 ? 1% cp 2200 pf 1000 pf d1 - d4 nihon inter electronics - ep05q03l, 11eqs03l, ec10qs04, ec10qs03l; motorola - mbr0540t1 0.22 f ? ? ? ?? r x line 1 k ? r r r r ? ? t x line r t r t rtipn rringn tringn ttipn ? ? 0.1 f gndtn vdddn vddt idt82v2048l one of eight identical channels vddt vddt d4 d3 d2 d1 2 : 1 1 2 : 1 1 1 k ? cp 3 2 a b note: 1. pulse t1124 transformer is recommended to be used in standard (std) operating temperature range (0c to 70c), while pulse t1114 transformer is recommended to be used in extended (ext) operating temperature range is -40c to +85c. see transformer specific ations table for details. 2. typical value. adjust for actual board parasitics to obtain optimum return loss. 3. common decoupling capacitor for all vddt and gndt pins. one per chip. 68 f table-7 transformer specifications (1) 1. pulse t1124 transformer is recommended to be used in standard (s td) operating temperature range (0 c to 70c), while pulse t111 4 transformer is recommended to be used in extended (ext) operating temperat ure range is -40c to +85c. electrical specification @ 25c part no. turns ratio (pri: sec 2%) ocl @ 25c (mh min) l l ( h max) c w/w (pf max) package/schematic std temp. ext temp. transmit receive transmit receive transmit receive transmit receive t1124 t1114 1:2ct 1ct:2 1.2 1.2 .6 .6 35 35 tou/3
16 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges 2.10 line protection in transmit side, the schottky diodes d1~d4 are required to protect the line driver and improve the design robustness. in receive side, the series resistors of 1 k ? are used to protect the receiver against current surges coupled in the device. the series resistors do not affect the receiver sensitivity, since the re ceiver impedance is as high as 120 k ? typically. 2.11 hitless protection switching (hps) the idt82v2048l transceivers include an output driver with high impedance feature for t1/e1 redundancy applications. this feature reduces the cost of redundancy protecti on by eliminating external relays. details of hps are described in relative application note. 2.12 transmit all ones (taos) in hardware mode, the taos mode is set by pulling pin tclkn high for more than 16 mclk cycles. in host mode, taos mode is set by programming register tao . in addition, automatic taos signals are inserted by setting register atao when loss of signal occurs. note that the taos generator adopts mclk as a timing reference. in order to assure that the output frequency is within specified limits, mclk must have the applicable stability. refer to figure-8 taos data path . figure-8 taos data path 2.13 g.772 monitoring the eight channels of idt82v2048l can all be configured to work as regular transceivers. in applicati ons using only seven channels (chan- nels 1 to 7), channel 0 is configured to non-intrusively monitor any of the other channels? inputs or outputs on t he line side. the monitoring is non- intrusive per itu-t g.772. figure-9 shows the monitoring principle. the receiver path or transmitter path to be monitored is configured by pin mc[3:0] in hardware mode or by pmon in host mode. the signal which is monitored can be observed digitally at the output pin rc0, rdp0 and rdn0. los detector is still in use in channel 0 for the monitored signal. in monitoring mode, a clock and dat a recovery circuit can be enabled for remote loopback operation. in remote loopback operation, the signal which is being monitored will be also output on ttip0 and tring0 pins. the output signal can then be connected to a standard test equipment for non-intrusive monito ring. rc0 pin will also output the recovered clock (dpll). the remote loopback is only av ailable in host mode operation. to enable the remote loopback, bit 0 in register rl0 has to be set, and bit 0 in register e-afe has to be cleared. t he register setting are: register rl0 set ?01?h, register e-afe set ?fe?h. for normal operation register rl0 has to be set ?00h? and register e- afe has to be set ?ffh?. slicer peak detector line driver waveform shaper los detector one of eight identical channels rtipn rringn ttipn tringn losn rcn rdpn rdnn tclkn tdnn tdpn transmit all ones
17 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges figure-9 monitoring principle 2.14 software reset writing register rs will cause software reset by initiating about 1 s reset cycle. this operation set all the registers to their default value. 2.15 power on reset during power up, an internal rese t signal sets all the registers to default values. the power-on reset ta kes at least 10 s, starting from when the power supply exceeds 2/3 vdda. 2.16 power down each transmit channel will be powered down by pulling pin tclkn low for more than 64 mclk cycles (i f mclk is available) or about 30 s (if mclk is not available). in hos t mode, each transmit channel will also be powered down by setting bit tpdnn in register e-tpdn to ?1?. all the receivers will be powered down when mclk is low. when mclk is clocked or high, se tting bit rpdnn in register e-rpdn to ?1? will configure the corresponding receiver to be powered down. 2.17 interface with 5 v logic the idt82v2048l can interface directly with 5 v ttl family devices. the internal input pads are tolerant to 5 v output from ttl and cmos family devices. slicer peak detector line driver waveform shaper los detector channel n ( 7 > n > 1 ) rtipn rringn ttipn tringn losn rcn rdpn rdnn tclkn tdnn tdpn g.772 monitor transmit all ones slicer peak detector line driver waveform shaper los detector channel 0 los0 rc0 rdp0 rdn0 tclk0 tdn0 tdp0 transmit all ones rtip0 rring0 ttip0 tring0 remote loopback cdr remote loopback
18 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges 2.18 host interface the host interface provides access to read and write the registers in the device. the interface consists of serial host interface and parallel host interface. by pulling pin mode2 to vddio/2 or high, the device can be set to work in serial mode and in parallel mode respectively. in host mode operation, expanded register e-fae has to be set to ?ffh? for proper device operation. see expanded register description on page 28 for details. 2.18.1 parallel host interface the interface is compatible with motorola and intel host. pins mode[1:0] are used to select the operating mode of the parallel host interface. when pin mode1 is pu lled low, the host uses separate address bus and data bus. when high, multiplexed address/data bus is used. when pin mode0 is pulled low, the parallel host interface is configured for motorola compatible hosts. when pin mode0 is pulled high, the parallel host interface is configured for intel compatible hosts. see table-1 pin description for more details. the host interface pins in each operation mode is tabulated in table-8 : figure-10 serial host mode timing 2.18.2 serial host interface by pulling pin mode2 to vddio/2, the device operates in the serial host mode. in this mode, the regist ers are accessible through a 16-bit word which contains an 8-bit command/address byte (bit r/ w and 5- address-bit a1~a5, a6 and a7 bits are ignored) and a subsequent 8-bit data byte (d7~d0), as shown in figure-10 . when bit r/ w is set to ?1?, data is read out from pin sdo. when bit r/ w is set to ?0?, data on pin sdi is written into the register whose address is indicated by address bits a5~a1. refer to figure-10 serial host mode timing . table-8 parallel host interface pins mode[2:0] host interface generic control, data and output pin 100 non-multiplexed motorola interface cs , ack , ds , r/ w , as , a[4:0], d[7:0], int 101 non-multiplexed intel interface cs , rdy, wr , rd , ale, a[4:0], d[7:0], int 110 multiplexed motorola interface cs , ack , ds , r/ w , as , ad[7:0], int 111 multiplexed intel interface cs , rdy, wr , rd , ale, ad[7:0], int a1 a3 a2 a4 a5 a6 d0 d1 d2 d3 d4 d5 d6 d7 r/ w d0 d1 d2 d3 d4 d5 d6 d7 a7 input data byte address/command byte high impedance driven while r/ w =1 sdi sdo sclk cs 1 22 1. while r/ w =1, read from idt82v2048l; while r/ w =0, write to idt82v2048l. 2. ignored.
19 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges 2.19 interrupt handling 2.19.1 interrupt sources there are two kinds of interrupt sources: 1. status change in register los . the analog/digital loss of signal detector continuously monitors the received signal to update the specific bit in register los which indicates presence or absence of a los condition. 2. status change in register df . the automatic power driver circuit continuously monitors the output drivers signal to update the specific bit in register dfm which indicates presence or absence of an output driver short circuit condition. figure-11 interru pt service routine 2.19.2 interrupt enable the idt82v2048l provides a latched interrupt output ( int ) and the two kinds of interrupts are all repor ted by this pin. when the interrupt mask register: losm and dfm , are set to ?1?, the interrupt status register: losi and dfi , are enabled respectively. whenever there is a transition (?0? to ?1? or ?1? to ?0?) in the corresponding status register, the interrupt status register will change into ?1?, which means an interrupt occurs, and there will be a high to low transition on int pin. an external pull-up resistor of approximately 10 k ? is required to support the wire- or operation of int . when any of the two interrupt mask registers is set to ?0? (the power-on default value is ?0?), the corresponding interrupt status register is disabled and t he transition on status register is ignored. 2.19.3 interrupt clearing when an interrupt occurs, the interrupt status registers: losi and dfi , are read to identify the interrupt source. these registers will be cleared to ?0? after the corresponding status registers: los and df are read. the status regi sters will be cleared onc e the corresponding condi- tions are met. pin int is pulled high when there is no pending interrupt left. the interrupt handling in the interrupt service routine is shown in figure-11 . service the interrupt read interrupt status register read corresponding status register interrupt allowed interrupt condition exist? yes no
20 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges 3 programming information 3.1 register list and map there are 18 primary registers (inc luding an address pointer control register and 4 expanded registers in the device). whatever the control interface is, 5 address bits are used to set the registers. in non-multiplexed paralle l interface mode, the five dedicated address bits are a[4:0]. in multiplexed parallel interface mode, ad[4:0] carries the address information. in se rial interface mode, a[5:1] are used to address the register. the register addp , addressed as 11111 or 1f hex, switches between primary registers bank and expanded registers bank. by setting register addp to ?aah?, the 5 address bits point to the expanded register bank, that is, 4 ex panded registers are available. by clearing register addp , the primary registers are available. 3.2 reserved and test registers primary registers, whose address are 01h, 0ch, 13h to 1eh, are reserved. expanded registers, whos e address are 00h, 01h, 05h, 06h, 08h to 0fh, are reserved. expanded registers, whose address are 10h to 1eh, are used for test and must be set to ?0? (default). table-9 primary register list address register r/w explanation hex serial interface a7-a1 parallel interface a7-a0 00 xx00000 xxx00000 id r device id register 01 xx00001 xxx00001 reserved 02 xx00010 xxx00010 rl0 r/w g.772 monitoring, remote loopback configuration register 03 xx00011 xxx00011 tao r/w transmit all ones configuration register 04 xx00100 xxx00100 los r loss of signal status register 05 xx00101 xxx00101 df r driver fault status register 06 xx00110 xxx00110 losm r/w los interrupt mask register 07 xx00111 xxx00111 dfm r/w driver fault interrupt mask register 08 xx01000 xxx01000 losi r los interrupt status register 09 xx01001 xxx01001 dfi r driver fault interrupt status register 0a xx01010 xxx01010 rs w software reset register 0b xx01011 xxx01011 pmon r/w performance monitor configuration register 0c xx01100 xxx01100 reserved 0d xx01101 xxx01101 lac r/w los/ais criteria configuration register 0e xx01110 xxx01110 atao r/w automatic taos configuration register 0f xx01111 xxx01111 gcf r/w global configuration register 10 xx10000 xxx10000 tsia r/w indirect address register for transmit template select 11 xx10001 xxx10001 ts r/w transmit template select register 12 xx10010 xxx10010 oe r/w output enable configuration register 13 xx10011 xxx10011 reserved 14 xx10100 xxx10100 15 xx10101 xxx10101 16 xx10110 xxx10110 17 xx10111 xxx10111 18 xx11000 xxx11000 19 xx11001 xxx11001 1a xx11010 xxx11010 1b xx11011 xxx11011 1c xx11100 xxx11100 1d xx11101 xxx11101 1e xx11110 xxx11110 1f xx11111 xxx11111 addp r/w address pointer control register for switching between primary register bank and expanded register bank
21 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges table-10 expanded (indirect address mode) register list address register r/w explanation hex serial interface a7-a1 parallel interface a7-a0 00 xx00000 xxx00000 reserved 01 xx00001 xxx00001 02 xx00010 xxx00010 e-afe r/w afe enable register 03 xx00011 xxx00011 e-rpdn r/w receiver n powerdown enable/disable register 04 xx00100 xxx00100 e-tpdn r/w transmitter n powerdown enable/disable register 05 xx00101 xxx00101 reserved 06 xx00110 xxx00110 07 xx00111 xxx00111 e-equa r/w enable equalizer enable/disable register 08 xx01000 xxx01000 reserved 09 xx01001 xxx01001 0a xx01010 xxx01010 0b xx01011 xxx01011 0c xx01100 xxx01100 0d xx01101 xxx01101 0e xx01110 xxx01110 0f xx01111 xxx01111 10 xx10000 xxx10000 test 11 xx10001 xxx10001 12 xx10010 xxx10010 13 xx10011 xxx10011 14 xx10100 xxx10100 15 xx10101 xxx10101 16 xx10110 xxx10110 17 xx10111 xxx10111 18 xx11000 xxx11000 19 xx11001 xxx11001 1a xx11010 xxx11010 1b xx11011 xxx11011 1c xx11100 xxx11100 1d xx11101 xxx11101 1e xx11110 xxx11110 1f xx11111 xxx11111 addp r/w address pointer control register for sw itching between primary register bank and expanded register bank
22 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges table-11 primary register map register address r/w default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 id 00h r default id 7 r 0 id 6 r 0 id 5 r 0 id 4 r 1 id 3 r 0 id 2 r 0 id 1 r 0 id 0 r 0 rl0 02h r/w default - r/w 0 - r/w 0 - r/w 0 - r/w 0 - r/w 0 - r/w 0 - r/w 0 rl0 r/w 0 tao 03h r/w default tao 7 r/w 0 tao 6 r/w 0 tao 5 r/w 0 tao 4 r/w 0 tao 3 r/w 0 tao 2 r/w 0 tao 1 r/w 0 tao 0 r/w 0 los 04h r default los 7 r 0 los 6 r 0 los 5 r 0 los 4 r 0 los 3 r 0 los 2 r 0 los 1 r 0 los 0 r 0 df 05h r default df 7 r 0 df 6 r 0 df 5 r 0 df 4 r 0 df 3 r 0 df 2 r 0 df 1 r 0 df 0 r 0 losm 06h r/w default losm 7 r/w 0 losm 6 r/w 0 losm 5 r/w 0 losm 4 r/w 0 losm 3 r/w 0 losm 2 r/w 0 losm 1 r/w 0 losm 0 r/w 0 dfm 07h r/w default dfm 7 r/w 0 dfm 6 r/w 0 dfm 5 r/w 0 dfm 4 r/w 0 dfm 3 r/w 0 dfm 2 r/w 0 dfm 1 r/w 0 dfm 0 r/w 0 losi 08h r default losi 7 r 0 losi 6 r 0 losi 5 r 0 losi 4 r 0 losi 3 r 0 losi 2 r 0 losi 1 r 0 losi 0 r 0 dfi 09h r default dfi 7 r 0 dfi 6 r 0 dfi 5 r 0 dfi 4 r 0 dfi 3 r 0 dfi 2 r 0 dfi 1 r 0 dfi 0 r 0 rs 0ah w default rs 7 w 1 rs 6 w 1 rs 5 w 1 rs 4 w 1 rs 3 w 1 rs 2 w 1 rs 1 w 1 rs 0 w 1 pmon 0bh r/w default - r/w 0 - r/w 0 - r/w 0 - r/w 0 mc 3 r/w 0 mc 2 r/w 0 mc 1 r/w 0 mc 0 r/w 0 lac 0dh r/w default lac 7 r/w 0 lac 6 r/w 0 lac 5 r/w 0 lac 4 r/w 0 lac 3 r/w 0 lac 2 r/w 0 lac 1 r/w 0 lac 0 r/w 0 atao 0eh r/w default atao 7 r/w 0 atao 6 r/w 0 atao 5 r/w 0 atao 4 r/w 0 atao 3 r/w 0 atao 2 r/w 0 atao 1 r/w 0 atao 0 r/w 0 gcf 0fh r/w default - r/w 0 - r/w 0 scpb r/w 0 - r/w 0 - r/w 0 - r/w 0 - r/w 0 - r/w 0 tsia 10 hex r/w default - r/w 0 - r/w 0 - r/w 0 - r/w 0 - r/w 0 tsia 2 r/w 0 tsia 1 r/w 0 tsia 0 r/w 0
23 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges ts 11 hex r/w default - r/w 0 - r/w 0 - r/w 0 - r/w 0 - r/w 0 ts 2 r/w 0 ts 1 r/w 0 ts 0 r/w 0 oe 12 hex r/w default oe 7 r/w 0 oe 6 r/w 0 oe 5 r/w 0 oe 4 r/w 0 oe 3 r/w 0 oe 2 r/w 0 oe 1 r/w 0 oe 0 r/w 0 addp 1f hex r/w default addp 7 r/w 0 addp 6 r/w 0 addp 5 r/w 0 addp 4 r/w 0 addp 3 r/w 0 addp 2 r/w 0 addp 1 r/w 0 addp 0 r/w 0 table-11 primary register map (continued) register address r/w default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
24 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges table-12 expanded (indirect address mode) register map register address r/w default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 e-afe (1) 1. in host mode, register e-afe has to be set to ?ffh? for proper device operation. see e-afe: afe enable selection register (r /w, expanded address = 02h) on page 28 for more details. 02h r/w default afe 7 r/w 0 afe 6 r/w 0 afe 5 r/w 0 afe 4 r/w 0 afe 3 r/w 0 afe 2 r/w 0 afe 1 r/w 0 afe 0 r/w 0 e-rpdn 03h r/w default rpdn 7 r/w 0 rpdn 6 r/w 0 rpdn 5 r/w 0 rpdn 4 r/w 0 rpdn 3 r/w 0 rpdn 2 r/w 0 rpdn 1 r/w 0 rpdn 0 r/w 0 e-tpdn 04h r/w default tpdn 7 r/w 0 tpdn 6 r/w 0 tpdn 5 r/w 0 tpdn 4 r/w 0 tpdn 3 r/w 0 tpdn 2 r/w 0 tpdn 1 r/w 0 tpdn 0 r/w 0 e-equa 07h r/w default equa 7 r/w 0 equa 6 r/w 0 equa 5 r/w 0 equa 4 r/w 0 equa 3 r/w 0 equa 2 r/w 0 equa 1 r/w 0 equa 0 r/w 0 addp 1fh r/w default addp 7 r/w 0 addp 6 r/w 0 addp 5 r/w 0 addp 4 r/w 0 addp 3 r/w 0 addp 2 r/w 0 addp 1 r/w 0 addp 0 r/w 0
25 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges 3.3 register description 3.3.1 primary registers id: device id register (r, address = 00h) symbol position default description id[7:0] id.7-0 10h an 8-bit word is pre-set into the device as the identification and revision number. this number is different with the functiona l changes and is mask programmed. rl0 : g.772 monitoring, remote loopback configur ation register (r/w, address = 02h) symbol position default description - rl.7-1 0000000 reserved rl[0] rl.0 0 0 = normal operation. (default) 1 = remote loopback enabled. tao : transmit all ones configurati on register (r/w, address = 03h) symbol position default description tao[7:0] tao.7-0 00h 0 = normal operation. (default) 1 = transmit all ones. los: loss of signal status r egister (r, address = 04h) symbol position default description los[7:0] los.7-0 00h 0 = normal operation. (default) 1 = loss of signal detected. df: driver fault status regi ster (r, address = 05h) symbol position default description df[7:0] df.7-0 00h 0 = normal operation. (default) 1 = driver fault detected. losm: loss of signal interrupt mask register (r/w, address = 06h) symbol position default description losm[7:0] losm.7-0 00h 0 = los interrupt is not allowed. (default) 1 = los interrupt is allowed. dfm: driver fault interrupt mask register (r/w, address = 07h) symbol position default description dfm[7:0] dfm.7-0 00h 0 = driver fault interrupt not allowed. (default) 1 = driver fault interrupt allowed. losi: loss of signal interrupt status register (r, address = 08h) symbol position default description losi[7:0] losi.7-0 00h 0 = (default). or after a los read operation. 1 = any transition on losn (corresponding losmn is set to ?1?).
26 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges dfi: driver fault interrupt status register (r, address = 09h) symbol position default description dfi[7:0] dfi.7-0 00h 0 = (default). or after a df read operation. 1 = any transition on dfn (corresponding dfmn is set to ?1?). rs: software reset register (w, address = 0ah) symbol position default description rs[7:0] rs.7-0 ffh writing to this register will not change the content in this register but initiate a 1 s reset cycle, which means all the registers in the device are set to their default values. pmon: performance monitor configurati on register (r/w, address = 0bh) symbol position default description - pmon.7-4 0000 0 = normal operation. (default) 1 = reserved. mc[3:0] pmon.3-0 0000 0000 = normal operation without monitoring (default) 0001 = monitor receiver 1 0010 = monitor receiver 2 0011 = monitor receiver 3 0100 = monitor receiver 4 0101 = monitor receiver 5 0110 = monitor receiver 6 0111 = monitor receiver 7 1000 = normal operation without monitoring 1001 = monitor transmitter 1 1010 = monitor transmitter 2 1011 = monitor transmitter 3 1100 = monitor transmitter 4 1101 = monitor transmitter 5 1110 = monitor transmitter 6 1111 = monitor transmitter 7 lac: los/ais criteria configuration register (r/w, address = 0dh) symbol position default description lac[7:0] lac.7-0 00h for e1 mode, the criterion is selected as below: 0 = g.775 (default) 1 = etsi 300 233 for t1 mode, the criterion meets t1.231. atao : automatic taos configuration register (r/w, address = 0eh) symbol position default description atao[7:0] atao.7-0 00h 0 = no automatic transmit all ones. (default) 1 = automatic transmit all ones to the line side during los.
27 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges gcf: global configuration regist er (r/w, address = 0fh) symbol position default description -gcf.7-600 0 = normal operation. 1 = reserved. scpb gcf.5 0 0 = short circuit protection is enabled. 1 = short circuit protection is disabled. - gcf.4-0 00000 0 = normal operation. 1 = reserved. tsia: indirect address register for transmit temp late select registers (r/w, address = 10h) symbol position default description - tsia.7-3 00000 0 = normal operation. (default) 1 = reserved. tsia[2:0] tsia.2-0 000 000 = channel 0 (default) 001 = channel 1 010 = channel 2 011 = channel 3 100 = channel 4 101 = channel 5 110 = channel 6 111 = channel 7 ts: transmit template select register (r/w, address = 11h) symbol position default description - ts.7-3 00000 0 = normal operation. (default) 1 = reserved. ts[2-0] ts.2-0 000 ts[2:0] pins select one of eight built-in transmit template for different applications. ts[2:0] mode cable length 000 e1 75 ? coaxial cable/120 ? twisted pair cable. 001 reserved. 010 011 t1 0 - 133 ft. 100 t1 133 - 266 ft. 101 t1 266 - 399 ft. 110 t1 399 - 533 ft. 111 t1 533 - 655 ft. oe: output enable configuration register (r/w, address = 12h) symbol position default description oe[7:0] oe.7-0 00h 0 = transmit drivers enabled. (default) 1 = transmit drivers in high impedance state. addp: address pointer control regi ster (r/w, address = 1f h) symbol position default description addp[7:0] addp.7-0 00h two kinds of configuration in this register can be set to sw itch between primary register bank and expanded register bank. when power up, the address pointer will point to the top address of primary register bank automatically. 00h = the address pointer points to the top address of primary register bank (default). aah = the address pointer points to the top address of expanded register bank.
28 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges 3.3.2 expanded register description e-afe: afe enable selection register (r/w, expanded address = 02h) symbol position default description afe[7:0] afe.7-0 00h (1) 1. in host mode, afe[7:0] bits must be set to ?ffh? for normal device operation. 0 = reserved (default) note: for remote loopback operation in g.772 monitoring mode, bit 0 can be set to '0'. 1 = afe mode enabled. e-rpdn: receiver n powerdown register (r/w, expanded address = 03h) symbol position default description rpdn[7:0] rpdn.7-0 00h 0 = normal operation. (default) 1 = receiver n is powered down. e-tpdn: transmitter n powerdown register (r/w, expanded address = 04h) symbol position default description tpdn[7:0] tpdn.7-0 00h 0 = normal operation. (default) 1 = transmitter n is powered down (1) (the corresponding transmit output driver enters a low power high impedance mode). 1. transmitter n is powered down w hen either pin tclkn is pulled low or tpdnn is set to ?1? e-equa: receive equalizer enable/disable register (r/w, expanded address = 07h) symbol position default description equa[7:0] equa.7-0 00h 0 = normal operation. (default) 1 = equalizer in receiver n is enabled, which can improve the receive performance when transmission length is more than 200 m.
29 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges 4 ieee std 1149.1 jtag test access port the idt82v2048l supports the digi tal boundary scan specification as described in the ieee 1149.1 standards. the boundary scan architecture cons ists of data and instruction registers plus a test access port (t ap) controller. control of the tap is achieved through signals applied to the tms and tck pins. data is shifted into the registers via the tdi pin, and shifted out of the registers via the tdo pin. jtag test data are clocked at a rate determined by jtag test clock. the jtag boundary scan registers includes bsr (boundary scan register), idr (device identification register), br (bypass register) and ir (instruction register). these will be described in the following pages. refer to figure-12 for architecture. 4.1 jtag instructions and instruction reg- ister (ir) the ir with instruction decode block is used to select the test to be executed or the data register to be accessed or both. the instructions are shifted in lsb first to this 3-bit register. see table-13 instruction register description on page 30 for details of the codes and the instructions related. figure-12 jtag architecture bsr (boundary scan register) idr (device identification register) br (bypass register) ir (instruction register) mux tdo tdi tck tms trst control<6:0> mux select high-z enable tap (test access port) controller parallel latched output digital output pins digital input pins
30 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges 4.2 jtag data register 4.2.1 device identification register (idr) the idr can be set to define the producer number, part number and the device revision, which can be us ed to verify the proper version or revision number that has been used in the system under test. the idr is 32 bits long and is partitioned as in table-14 . data from the idr is shifted out to tdo lsb first. 4.2.2 bypass register (br) the br consists of a single bit. it can provide a serial path between the tdi input and tdo output, bypassi ng the bsr to reduce test access times. 4.2.3 boundary scan register (bsr) the bsr can apply and read test patterns in parallel to or from all the digital i/o pins. the bsr is a 98 bits long shift register and is initialized and read using the instruction extest or sample/preload. each pin is related to one or more bits in the bsr. please refer to table-15 for details of bsr bits and their functions. table-13 instruction register description ir code instruction comments 000 extest the external test instruction allows testing of the interconnection to other devices. when the current instruction is the extest instruction, the boundary scan register is placed between tdi and tdo. the signal on the input pins can be sampled by loading the boundary scan register using the captur e-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. the signal on the output pins can be controlled by loading patterns shifted in through input tdi into the boundary scan register using the update-dr state. 100 sample/preload the sample instruction samples all the device inputs and outputs. for this instruction, the boundary scan register is placed between tdi and tdo. the normal path between idt82v2048l logic and the i/o pins is maintained. primary device inputs and outputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled val- ues can then be viewed by shifting the boundary scan register using the shift-dr state. 110 idcode the identification instruction is used to connect the identification register between tdi and tdo. the device's identifica- tion code can then be shifted out using the shift-dr state. 111 bypass the bypass instruction shifts data from input tdi to output tdo with one tck clock period delay. the instruction is used to bypass the device. table-14 device identification register description bit no. comments 0set to ?1? 1~11 producer number 12~27 part number 28~31 device revision table-15 boundary scan register description bit no. bit symbol pin signal type comments 0pout0 d0 i/o 1 pin0 d0 i/o 2pout1 d1 i/o 3 pin1 d1 i/o 4pout2 d2 i/o 5 pin2 d2 i/o 6pout3 d3 i/o 7 pin3 d3 i/o 8pout4 d4 i/o 9 pin4 d4 i/o 10 pout5 d5 i/o 11 pin5 d5 i/o 12 pout6 d6 i/o 13 pin6 d6 i/o 14 pout7 d7 i/o 15 pin7 d7 i/o
31 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges 16 pios n/a - controls pins d[7:0]. when ?0?, the pins are configured as outputs. the output values to the pins are set in pout 7~0. when ?1?, the pins are in high impedance. the input values to the pins are read in pin 7~0. 17 tclk1 tclk1 i 18 tdp1 tdp1 i 19 tdn1 tdn1 i 20 rc1 rc1 o 21 rdp1 rdp1 o 22 rdn1 rdn1 o 23 hzen1 n/a - controls pin rdp1, rdn1 and rc1. when ?0?, the outputs are enabled on the pins. when ?1?, the pins are in high impedance. 24 los1 los1 o 25 tclk0 tclk0 i 26 tdp0 tdp0 i 27 tdn0 tdn0 i 28 rc0 rc0 o 29 rdp0 rdp0 o 30 rdn0 rdn0 o 31 hzen0 n/a - controls pin rdp0, rdn0 and rc0. when ?0?, the outputs are enabled on the pins. when ?1?, the pins are in high impedance. 32 los0 los0 o 33 mode1 mode1 i 34 los3 los3 o 35 rdn3 rdn3 o 36 rdp3 rdp3 o 37 hzen3 n/a - controls pin rdp3, rdn3 and rc3. when ?0?, the outputs are enabled on the pins. when ?1?, the pins are in high impedance. 38 rc3 rc3 o 39 tdn3 tdn3 i 40 tdp3 tdp3 i 41 tclk3 tclk3 i 42 los2 los2 o 43 rdn2 rdn2 o 44 rdp2 rdp2 o 45 hzen2 n/a - controls pin rdp2, rdn2 and rc2. when ?0?, the outputs are enabled on the pins. when ?1?, the pins are in high impedance. 46 rc2 rc2 o 47 tdn2 tdn2 i 48 tdp2 tdp2 i 49 tclk2 tclk2 i 50 int int o 51 ack ack o 52 sdordys n/a - control pin ack . when ?0?, the output is enabled on pin ack . when ?1?, the pin is in high impedance. 53 wrb ds i 54 rdb r/ w i 55 ale ale i table-15 boundary scan regi ster description (continued) bit no. bit symbol pin signal type comments
32 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges 56 csb cs i 57 mode0 mode0 i 58 tclk5 tclk5 i 59 tdp5 tdp5 i 60 tdn5 tdn5 i 61 rc5 rc5 o 62 rdp5 rdp5 o 63 rdn5 rdn5 o 64 hzen5 n/a - controls pin rdp5, rdn5 and rc5. when ?0?, the outputs are enabled on the pins. when ?1?, the pins are in high impedance. 65 los5 los5 o 66 tclk4 tclk4 i 67 tdp4 tdp4 i 68 tdn4 tdn4 i 69 rc4 rc4 o 70 rdp4 rdp4 o 71 rdn4 rdn4 o 72 hzen4 n/a - controls pin rdp4, rdn4 and rc4. when ?0?, the outputs are enabled on the pins. when ?1?, the pins are in high impedance. 73 los4 los4 o 74 oe oe i 75 clke clke i 76 los7 los7 o 77 rdn7 rdn7 o 78 rdp7 rdp7 o 79 hzen7 n/a - controls pin rdp7, rdn7 and rc7. when ?0?, the outputs are enabled on the pins. when ?1?, the pins are in high impedance. 80 rc7 rc7 o 81 tdn7 tdn7 i 82 tdp7 tdp7 i 83 tclk7 tclk7 i 84 los6 los6 o 85 rdn6 rdn6 o 86 rdp6 rdp6 o 87 hzen6 n/a - controls pin rdp6, rdn6 and rc6. when ?0?, the outputs are enabled on the pins. when ?1?, the pins are in high impedance. 88 rc6 rc6 o 89 tdn6 tdn6 i 90 tdp6 tdp6 i 91 tclk6 tclk6 i 92 mclk mclk i 93 mode2 mode2 i 94 a4 a4 i 95 a3 a3 i 96 a2 a2 i 97 a1 a1 i 98 a0 a0 i table-15 boundary scan regi ster description (continued) bit no. bit symbol pin signal type comments
33 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges 4.3 test access po rt controller the tap controller is a 16-st ate synchronous state machine. figure- 13 shows its state diagram a descripti on of each state follows. note that the figure contains two main branc hes to access either the data or instruction registers. the value s hown next to each state transition in this figure states the value present at tms at each rising edge of tck. refer to table-16 for details of the state description. table-16 tap controller state description state description test logic reset in this state, the test logic is disabled. the device is set to normal operation. during initialization, the device initializes the instruction register with the idcode instruction. regardless of the original state of the controller, the controlle r enters the test-logic-reset state when the tms input is held high for at least 5 rising edges of tck. the controller remains in this state while tms is high. the device processor automatically enters this sta te at power-up. run-test/idle this is a controller state between scan operations. once in this state, the controller remains in the state as long as tms is h eld low. the instruction register and all test data registers retain their previous state. when tms is high and a rising edge is applied to tck, the controller moves to the select-dr state. select-dr-scan this is a temporary controller state and the instruction does not change in this state. the test data register selected by the current instruction retains its previous state. if tms is held low and a rising edge is applied to tck when in this state, the controller moves int o the capture-dr state and a scan sequence for the selected test data register is initiated. if tms is held high and a rising edge applied to tc k, the controller moves to the select-ir-scan state. capture-dr in this state, the boundary scan register captures input pin data if the current instruction is extest or sample/preload. the i nstruction does not change in this state. the other test data registers, which do not have parallel input, are not changed. when the tap c ontroller is in this state and a rising edge is applied to tck, the controller enters the exit1-dr state if tms is high or the shift-dr state i f tms is low. shift-dr in this controller state, the test data register connected between tdi and tdo as a result of the current instruction shifts da ta on stage toward its serial output on each rising edge of tck. the instruction does not change in this state. when the tap controller is in this state and a rising edge is applied to tck, the controller enters the exit1-dr state if tms is high or remains in the shift-dr state if tms is low. exit1-dr this is a temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller to ente r the update-dr state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the pause-dr state. the test data register selected by the current instruction retains its previous value and the instruction does not chang e during this state. pause-dr the pause state allows the test controller to temporarily halt the shifting of data through the test data register in the seria l path between tdi and tdo. for example, this state could be used to allow the tester to reload its pin memory from disk during application of a l ong test sequence. the test data register selected by the current instruction retains its previous value and the instruction does not ch ange during this state. the controller remains in this state as long as tms is low. when tms goes high and a rising edge is applied to tck, the controller moves to the exit2-dr state. exit2-dr this is a temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller to ente r the update-dr state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the shift-dr state. the test data register selected by the current instruction retains its previous value and the instruction does not change durin g this state. update-dr the boundary scan register is provided with a latched parallel output to prevent changes while data is shifted in response to t he extest and sample/preload instructions. when the tap controller is in this state and the boundary scan register is selected, data is l atched into the parallel output of this register from the shift-register path on the falling edge of tck. the data held at the latched para llel output changes only in this state. all shift-register stages in the test data register selected by the current instruction retain their previo us value and the instruc- tion does not change during this state. select-ir-scan this is a temporary controller state. the test data register selected by the current instruction retains its previous state. if tms is held low and a rising edge is applied to tck when in this state, the contro ller moves into the capture-ir state, and a scan sequence for the instruction reg- ister is initiated. if tms is held high and a rising edge is applied to tck, the controller moves to the test-logic-reset state . the instruction does not change during this state. capture-ir in this controller state, the shift register contained in the instruction register loads a fixed value of ?100? on the rising e dge of tck. this sup- ports fault-isolation of the board-level serial test data path. data registers selected by the current instruction retain their value and the instruc- tion does not change during this state. when the controller is in this state and a rising edge is applied to tck, the controlle r enters the exit1- ir state if tms is held high, or the shift-ir state if tms is held low. shift-ir in this state, the shift register contained in the instruction register is connected between tdi and tdo and shifts data one st age towards its serial output on each rising edge of tck. the test data register selected by the current instruction retains its previous value and the instruction does not change during this state. when the controller is in this state and a rising edge is applied to tck, the controller ent ers the exit1-ir state if tms is held high, or remains in the shift-ir state if tms is held low.
34 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges figure-13 jtag state diagram exit1-ir this is a temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller to ente r the update-ir state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the pause-ir state. the test data register selected by the current instruction retains its previous value and the instruction does not change durin g this state. pause-ir the pause state allows the test controller to temporarily halt the shifting of data through the instruction register. the test data register selected by the current instruction retains its previous value and the instruction does not change during this state. the controller rem ains in this state as long as tms is low. when tms goes high and a rising edge is applied to tck, the controller moves to the exit2-ir state. exit2-ir this is a temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller to ente r the update-ir state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the shift-ir state. the test data register selected by the current instruction retains its previous value and the instruction does not change durin g this state. update-ir the instruction shifted into the instruction register is latched into the parallel output from the shift-register path on the f alling edge of tck. when the new instruction has been latched, it becomes the current instruction. the test data registers selected by the current instruction retain their previous value. table-16 tap controller stat e description (continued) state description test-logic reset run test/idle select-dr select-ir capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 0 1 1 1 00 00 0 0 1 1 1 0 1 0 1 1 1 0 1 0 1 0 1 1 0 0 0 1
35 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges absolute maximum rating recommended operating conditions symbol parameter min max unit vdda, vddd core power supply -0.5 4.0 v vddio0, vddio1 i/o power supply -0.5 4.0 v vddt0-7 transmit power supply -0.5 7.0 v vin input voltage, any digital pin gnd-0.5 5.5 v input voltage (1) , rtipn pins and rringn pins 1. referenced to ground gnd-0.5 vdda+ 0.5 vddd+ 0.5 v v esd voltage, any pin (2) 2. human body model 2000 v iin transient latch-up current, any pin 100 ma input current, any digital pin (3) 3. constant input current -10 10 ma dc input current, any analog pin (3) 100 ma pd maximum power dissipation in package 1.6 w ts storage temperature -65 +150 c caution : exceeding these values may cause permanent damage. functional operation under these conditions is not implied. exposure to ab solute maximum rat- ing conditions for extended periods may affect device reliability. symbol parameter min typ max unit vdda, vddd core power supply 3.13 3.3 3.47 v vddio i/o power supply 3.13 3.3 3.47 v vddt (1) 1. t1 is only 5v vddt. transmitter supply 3.3 v 3.13 3.3 3.47 v 5 v 4.75 5.0 5.25 v t a ambient operating temperature -40 25 85 c r l output load at ttipn pins and tringn pins 25 ? i vdd average core power supply current (2) 2. maximum power and current consumption over the full operating temperature and power supply vo ltage range. includes all channels . 55 65 ma i vddio i/o power supply current (3) 3. digital output is driving 50 pf load, digita l input is within 10% of the supply rails. 15 25 ma i vddt average transmitter power supply current, t1 mode (2),(4),(5) 4. t1 maximum values measured with maximum c able length (len = 111). typical values meas ured with typical cable length (len = 101) . 5. power consumption includes power absorbed by line load and external transmitter components. 50% ones density data: 230 ma 100% ones density data: 440 ma
36 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges power consumption dc characteristics symbol parameter len min typ max (1)(2) 1. maximum power and current consumption over the full operating temperature and power supply volt age range. includes all channels . 2. power consumption includes power absorbed by line load and external transmitter components. unit e1, 3.3 v, 75 ? load 50% ones density data: 100% ones density data: 000 000 - - 662 1100 - 1177 mw mw e1, 3.3 v, 120 ? load 50% ones density data: 100% ones density data: 000 000 - - 576 930 - 992 mw mw e1, 5.0 v, 75 ? load 50% ones density data: 100% ones density data: 000 000 - - 910 1585 - 1690 mw mw e1, 5.0 v, 120 ? load 50% ones density data: 100% ones density data: 000 000 - - 785 1315 - 1410 mw mw t1, 5.0 v, 100 ? load (3) 50% ones density data: 100% ones density data: 3. t1 maximum values measured with maximum cable length (len = 111). typical values me asured with typical cable length (len = 101) . 101 111 - - 1185 2395 - 2670 mw mw symbol parameter min typ max unit v il input low level voltage mode2 and dn pins vddio-0.2 v all other digital inputs pins 0.8 v v im input mid level voltage mode2 and dn pins vddio+0.2 vddio vddio-0.2 v v ih input high voltage mode2 and dn pins vddio+ 0.2 v all other digital inputs pins 2.0 v v ol output low level voltage (1) (iout = 1.6 ma) 1. output drivers will output cmos logic levels into cmos loads. 0.4 v v oh output high level voltage (1) (iout = 400 a) 2.4 vddio v v ma analog input quiescent voltage (rtipn/rringn pin while floating) 1.33 1.4 1.47 v i h input high level current (mode2 and dn pins) 50 a i l input low level current (mode2 and dn pins) 50 a i i input leakage current tms, tdi and trst pins all other digital input pins -10 50 10 a a i zl high impedance leakage current -10 10 a z oh output high impedance on ttipn and tringn pins 150 k ? 1 3 --- 1 3 --- 1 2 --- 2 3 --- 2 3 ---
37 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges transmitter characteristics symbol parameter min typ max unit v o-p output pulse amplitudes (1) e1, 75 ? load e1, 120 ? load t1, 100 ? load 1. e1: measured at the line output ports; t1: measured at the dsx 2.14 2.7 2.4 2.37 3.0 3.0 2.6 3.3 3.6 v v v v o-s zero (space) level e1, 75 ? load e1, 120 ? load t1, 100 ? load -0.237 -0.3 -0.15 0.237 0.3 0.15 v v v transmit amplitude variation with supply -1 +1 % difference between pulse sequences for 17 consecutive pulses 200 mv t pw output pulse width at 50% of nominal amplitude e1: t1: 232 338 244 350 256 362 ns ns ratio of the amplitudes of positive and negative pulses at the center of the pulse interval 0.95 1.05 rtx transmit return loss (2) 2. test at idt82v2048l evaluation board e1, 75 ? 51 khz ? 102 khz 102 khz ? 2.048 mhz 2.048 mhz ? 3.072 mhz 15 15 15 db db db e1, 120 ? 51 khz ? 102 khz 102 khz ? 2.048 mhz 2.048 mhz ? 3.072 mhz 15 15 15 db db db t1 (vddt = 5 v) 51 khz ? 102 khz 102 khz ? 2.048 mhz 2.048 mhz ? 3.072 mhz 15 15 15 db db db td transmit path delay 3 u.i. i sc line short circuit current (3) 3. measured on device, between ttipn and tringn 180 map
38 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges receiver characteristics symbol parameter min typ max unit att permissible cable attenuation (e1: @ 1024 khz, t1: @ 772 khz) 15 db ia input amplitude 0.1 0.9 vp sir signal to interference ratio margin (1) 1. e1: per g.703, o.151 @ 6 db cable attenuation. t1: @ 655 ft. of 22 abam cable -15 db sre data decision threshold (refer to peak input voltage) 50 % data slicer threshold 150 mv analog loss of signal (2) declare/clear: 2. measured on device, between rtipn and rringn, all ones signal 120/150 200/250 280/350 mvp allowable consecutive zeros before los e1, g.775: e1, etsi 300 233: t1, t1.231-1993 32 2048 175 los reset clock recovery mode 12.5 % ones jrx p-p peak to peak intrinsic receive jitter (ja disabled) e1 (wide band): t1 (wide band): 0.0625 0.0625 u.i. u.i. zdm receiver differential input impedance 120 k ? zcm receiver common mode input impedance to gnd 10 k ? rrx receive return loss 51 khz ? 102 khz 102 khz ? 2.048 mhz 2.048 mhz ? 3.072 mhz 20 20 20 db db db receive path delay 3 u.i.
39 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges transceiver timing characteristics symbol parameter min typ max unit mclk frequency e1: t1: 2.048 1.544 mhz mhz mclk tolerance -100 100 ppm mclk duty cycle 40 60 % transmit path tclk frequency e1: t1: 2.048 1.544 mhz mhz tclk tolerance -50 +50 ppm tclk duty cycle 10 90 % t1 transmit data setup time 40 ns t2 transmit data hold time 40 ns delay time of oe low to driver high impedance 1s delay time of tclk low to driver high impedance 40 44 48 s receive path t4 rdn/rdp pulse width (1) 1. 0 db cable loss e1: t1: 200 300 244 324 ns ns t5 rx data prop. delay (2) 2. 15 pf load 40 ns t6 receive rise time (2) 14 ns t7 receive fall time (2) 12 ns
40 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges figure-14 transmit system interface timing figure-15 receive system interface timing tdnn tdpn tclkn t1 t2 rtipn, rringn rdpn rdnn t5 t5 t4 t6 t7 t4 t6 t7 (clke = 1) (clke = 1) t4 t4 t6 t7 t4 xor, rdpn + rdnn rdpn rdnn t5 t4 t6 t7 t4 t6 t7 (clke = 0) (clke = 0) t5
41 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges jtag timing characteristics figure-16 jtag interface timing symbol parameter min typ max unit comments t1 tck period 200 ns t2 tms to tck setup time tdi to tck setup time 50 ns t3 tck to tms hold time tck to tdi hold time 50 ns t4 tck to tdo delay time 100 ns tck t1 t2 t3 tdo tms tdi t4
42 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges parallel host interface timing characteristics intel mode read timing characteristics symbol parameter min typ max unit comments t1 active rd pulse width 90 ns (1) 1. the t1 is determined by the start time of the valid data when the rdy signal is not used. t2 active cs to active rd setup time 0 ns t3 inactive rd to inactive cs hold time 0 ns t4 valid address to inactive ale setup time (in multiplexed mode) 5 ns t5 invalid rd to address hold time (in non-multiplexed mode) 0 ns t6 active rd to data output enable time 7.5 15 ns t7 inactive rd to data high impedance delay time 7.5 15 ns t8 active cs to rdy delay time 6 12 ns t9 inactive cs to rdy high impedance delay time 6 12 ns t10 inactive rd to inactive int delay time 20 ns t11 address latch enable pulse width (in multiplexed mode) 10 ns t12 address latch enable to rd setup time (in multiplexed mode) 0 ns t13 address setup time to valid data time (in non-multiplexed mode) 18 32 ns t14 inactive rd to active rdy delay time 10 15 ns t15 active rd to active rdy delay time 30 85 ns t16 inactive ale to address hold time (in multiplexed mode) 5 ns
43 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges figure-17 non-multiplexed intel mode read timing figure-18 multiplexed intel mode read timing int rdy d[7:0] a[4:0] ale(=1) rd cs t1 t2 t3 t5 t6 t7 t8 t9 t10 t13 address data out t14 t15 int rdy ad[7:0] ale rd cs t1 t2 t3 t6 t7 t8 t9 t10 t4 t11 t12 address data out t15 t14 t16 t13
44 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges intel mode write timing characteristics figure-19 non-multiplexe d intel mode write timing figure-20 multiplexed intel mode write timing symbol parameter min typ max unit comments t1 active wr pulse width 90 ns (1) 1. the t1 can be 15 ns when rdy signal is not used. t2 active cs to active wr setup time 0 ns t3 inactive wr to inactive cs hold time 0 ns t4 valid address to latch enable setup time (in multiplexed mode) 5 ns t5 invalid wr to address hold time (in non-multiplexed mode) 2 ns t6 valid data to inactive wr setup time 5 ns t7 inactive wr to data hold time 10 ns t8 active cs to inactive rdy delay time 6 12 ns t9 active wr to active rdy delay time 30 85 ns t10 inactive wr to inactive rdy delay time 10 15 ns t11 invalid cs to rdy high impedance delay time 6 12 ns t12 address latch enable pulse width (in multiplexed mode) 10 ns t13 inactive ale to wr setup time (in multiplexed mode) 0 ns t14 inactive ale to address hold time (in multiplexed mode) 5 ns t15 address setup time to inactive wr time (in non-multiplexed mode) 5 ns rdy d[7:0] a[4:0] ale(=1) wr cs t2 t1 t3 t5 t6 t7 t8 t9 t10 t11 address write data t15 rdy ad[7:0] ale wr cs t1 t2 t3 t6 t7 t8 t9 t10 t4 t12 t13 write data address t11 t14
45 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges motorola mode read timing characteristics figure-21 non-multiplexed motorola mode read timing figure-22 multiplexed motorola mode read timing symbol parameter min typ max unit comments t1 active ds pulse width 90 ns (1) 1. the t1 is determined by the start time of the valid data when the ack signal is not used. t2 active cs to active ds setup time 0 ns t3 inactive ds to inactive cs hold time 0 ns t4 valid r/ w to active ds setup time 0 ns t5 inactive ds to r/ w hold time 0.5 ns t6 valid address to active ds setup time (in non-multiplexed mode) 5 ns t7 active ds to address hold time (in non-multiplexed mode) 10 ns t8 active ds to data valid delay time (in non-multiplexed mode) 20 35 ns t9 active ds to data output enable time 7.5 15 ns t10 inactive ds to data high impedance delay time 7.5 15 ns t11 active ds to active ack delay time 30 85 ns t12 inactive ds to inactive ack delay time 10 15 ns t13 inactive ds to invalid int delay time 20 ns t14 active as to active ds setup time (in multiplexed mode) 5 ns int ack d[7:0] a[4:0] ale(=1) ds cs t1 address data out r/ w t2 t3 t4 t5 t6 t8 t10 t11 t12 t13 t7 t9 int ack ad[7:0] as ds cs data out address r/ w t1 t2 t3 t4 t5 t6 t7 t8 t11 t10 t12 t13 t14 t9
46 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges motorola mode write timing characteristics figure-23 non-multiplexed motorola mode write timing figure-24 multiplexed mo torola mode writing timing symbol parameter min typ max unit comments t1 active ds pulse width 90 ns (1) 1. the t1 can be 15ns when the ack signal is not used. t2 active cs to active ds setup time 0 ns t3 inactive ds to inactive cs hold time 0 ns t4 valid r/ w to active ds setup time 10 ns t5 inactive ds to r/ w hold time 0 ns t6 valid address to active ds setup time (in non-multiplexed mode) 10 ns t7 valid ds to address hold time (in non-multiplexed mode) 10 ns t8 valid data to inactive ds setup time 5 ns t9 inactive ds to data hold time 10 ns t10 active ds to active ack delay time 30 85 ns t11 inactive ds to inactive ack delay time 10 15 ns t12 active as to active ds (in multiplexed mode) 0 ns t13 inactive ds to inactive as hold time (in multiplexed mode) 15 ns ack d[7:0] a[4:0] ale(=1) ds cs t1 address write data r/ w t2 t3 t4 t6 t7 t5 t8 t9 t10 t11 ack ad[7:0] as ds cs write data address r/ w t1 t2 t3 t4 t5 t6 t7 t8 t9 t13 t10 t11 t12
47 idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges serial host interface timing characteristics figure-25 serial interface write timing figure-26 serial interface read timing with clke = 0 figure-27 serial interface read timing with clke = 1 symbol parameter min typ max unit comments t1 sclk high time 25 ns t2 sclk low time 25 ns t3 active cs to sclk setup time 10 ns t4 last sclk hold time to inactive cs time 50 ns t5 cs idle time 50 ns t6 sdi to sclk setup time 5 ns t7 sclk to sdi hold time 5 ns t8 rise/fall time (any pin) 100 ns t9 sclk rise and fall time 50 ns t10 sclk to sdo valid delay time 25 35 ns load = 50 pf t11 sclk falling edge to sdo high impedance hold time (clke = 0) or cs rising edge to sdo high impedance hold time (clke = 1) 100 ns msb lsb lsb cs sclk sdi t1 t2 t3 t4 t5 t6 t7 t7 control byte data byte 12345678910111213141516 7 6 5 4 3 2 1 0 sdo cs sclk t4 t11 t10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 7 6 5 4 3 2 1 0 sdo cs sclk t4 t11 t10
idt82v2048l octal t1/e1 short haul analog front end industrial temperature ranges idt and the idt logo are trademarks of integrated device technology, inc. 48 corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com for sales: 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 for tech support: 408-360-1552 email:telecomhelp@idt.com ordering information datasheet document history 07/29/2005 pgs. 1, 4, 5, 7 to 10, 13, 15 to 17, 19, 20, 22, 23, 25, 25, 28, 32, 35, 37 to 40, 43 to 47 idt xxxxxxx xx x device type blank process/ temperature range bb 82v2048l industrial (-40 c to + 85 c) plastic ball grid array (pbga, bb160) t1/e1 short haul analog front end da thin quad flatpack (tqfp, da144) bbg green plastic ball grid array (pbga, bbg160) dag green thin quad flatpack (tqfp, dag144) package

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